In semiconductor device manufacturing, 3D monolithic designs may include stacked layers of devices (e.g., field effect transistor (FET) devices) that are sequentially processed to reduce a device footprint. For example, a FET-over-FET integration scheme is one form of 3D monolithic integration in which p-type and n-type FET devices are separately formed on different device layers of a 3D monolithic semiconductor IC device. The separation of p-type and n-type FET devices provides certain advantages such as the ability to use more optimal or compatible semiconductor materials (e.g., germanium, silicon-germanium, silicon, III-V compound semiconductor material, etc.) on different layers to enhance or otherwise optimize device performance. In such cases and especially for devices with p-type FETs over n-type FETs or vice versa, a significant amount of interlayer via contacts are needed to make a functional integrated circuit. In this regard, the interlayer via contacts can consume a large amount of surface area and thereby diminish the scaling benefits of the 3D monolithic approach.